To provide a switching circuit capable of simultaneously suppressing both a switching loss and a surge voltage.
The present invention relates to a switching circuit for temporally switching main electrodes of a transistor between a conducted state and a non-conducted state by switching a gate voltage of the transistor, wherein a drain or a collector of the transistor and its gate or the drain or the collector of the transistor and its source or its emitter are connected by a series circuit of a Zener diode and a capacitor. While a drain voltage is low, a state is judged where capacitance of the capacitor is not contributed by the Zener diode, a drain current and the drain voltage vary at high speed, thereby reducing the switching loss. When the drain voltage increases, the Zener diode surrenders, the capacitance of the capacitor is added and the drain current and the drain voltage vary at a low speed, thereby suppressing the surge voltage low.
COPYRIGHT: (C)2008,JPO&INPIT
KUWABARA MAKOTO
OKADA KYOKO
MIZUNO SHOJI
AOKI TAKAAKI
DENSO CORP
| JPH0225107A | 1990-01-26 | |||
| JPH0870572A | 1996-03-12 | |||
| JPH03136412A | 1991-06-11 |