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Patent Searching and Data


Title:
UP/DOWN SWITCHING CIRCUIT
Document Type and Number:
Japanese Patent JPS62241430
Kind Code:
A
Abstract:

PURPOSE: To improve versatility and the degree of integration by composing a switching circuit of two flip-flop circuits and a gate circuit without using any differentiating circuit.

CONSTITUTION: Pulse signals which, are about 90° out of phase with each other and have the same waveform are inputted to input terminals 9a and 9b of a decoder 9 and one of output terminals Q0∼Q3 is held at a level '1' according to the level states of the input signals. For example, when both inputs of the decoder 9 are '0' and its output Q0 is 'l', the output of the OR gate 10 is '1' and the flip-flop circuits(F.F) 11 and 12 are in a reset state. Consequently, the outputs of AND gates 13 and 14 are held at the level '0'. This circuit eliminates the need to set the time constant of a one-shot multivibrator independently unlike before. Further, a decrease in the degree of integration which is caused by an element determining the time constant is eliminated.


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Inventors:
SHIBATA HIROMI
TODA ATSUSHI
Application Number:
JP8434286A
Publication Date:
October 22, 1987
Filing Date:
April 14, 1986
Export Citation:
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Assignee:
KOITO MFG CO LTD
International Classes:
H03K21/02; G01D5/244; G01D5/245; H03K23/00; H03K23/86; (IPC1-7): H03K21/02; H03K23/86
Domestic Patent References:
JPS58220528A1983-12-22
Attorney, Agent or Firm:
Masaki Yamakawa