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Title:
SWITCHING ELEMENT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3447627
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To improve mounting density as for a reconfigurable circuit.
SOLUTION: This switching element is provided with a buffer R for amplifying a signal inputted from an input terminal N1 to output the resultant signal to an output terminal N2, first to eighth transistors T1 to T8 respectively provided between the input terminal and a first wire L1, between the input terminal and a second wire L2, between the input terminal and a third wire L3, between the input terminal and a fourth wire L4, between the output terminal and the first wire, between the output terminal and the second wire, between the output terminal and the third wire and between the output terminal and the fourth wire, and first to eighth memories M1 to M8 respectively storing data for controlling the conductive state of the first to eighth transistors.


Inventors:
Kazunori Ouchi
Application Number:
JP24823499A
Publication Date:
September 16, 2003
Filing Date:
September 02, 1999
Export Citation:
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Assignee:
Toshiba Corporation
International Classes:
H01L21/82; H03K19/177; (IPC1-7): H03K19/177; H01L21/82
Domestic Patent References:
JP926870A
JP3191319A
JP1321726A
JP3132212A
Attorney, Agent or Firm:
Hideaki Togawa