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Patent Searching and Data


Title:
SYNCHRONIZATION CONTOL SYSTEM
Document Type and Number:
Japanese Patent JPH0685806
Kind Code:
A
Abstract:

PURPOSE: To obtain the synchronization control system in which increase in redundant bits is suppressed.

CONSTITUTION: The synchronization control system is provided with a coding circuit 101 coding information and a decoding circuit 102 decoding the original information from the coded information. Then the coding circuit 101 has an algebraic multiplexer means applying algebraic multiplexing to a transmission information bit string and a control information bit string known to a decoder to generate a multiplexed signal by using a multiplexing/demultiplexing code specific to the bit strings and known to the decoder. Moreover, the decoding circuit 102 has an algebraic demultiplexer means demultiplexing the transmission bit information string and the said control information bit string algebraically from the multiplexed signal by using a specific multiplexer/demultiplexer code to recover the bit strings and has a synchronization control means applying synchronization control to the signal of the transmission information bit string based on a difference between the recovered control information bit string and the known control information bit string.


Inventors:
YAMAZAKI SHOICHIRO
Application Number:
JP23169092A
Publication Date:
March 25, 1994
Filing Date:
August 31, 1992
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H04J3/06; H04J99/00; H04L1/00; H04L1/16; H04L7/08; H04J3/00; (IPC1-7): H04L7/08; H04J3/00; H04J3/06; H04J15/00; H04L1/00; H04L1/16
Attorney, Agent or Firm:
Suyama Saichi