Title:
SYNCHRONIZATION DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3769833
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve an output accuracy by increasing an operation limit frequency of a synchronization detection circuit configured on an integrated circuit.
SOLUTION: An inverting amplifier circuit 12 to generate an inverting signal being an inverse of an input signal Sin is provided to one path in two systems of signal paths from an input terminal Tim reaching an output terminal Tout, and a buffer circuit 14 providing an output of a noninverting signal in phase to the Sin is provided to the other path. Moreover, CMOS analog switches 16, 18 are provided to outputs of each of the circuits 12, 14. Then each of the analog switches 16, 18 is alternately turned on/off by control signals &phiv 1, &phiv 1 generated from a reference signal Sc and when the Sc is higher than a zero cross point voltage Vt1, a noninverting signal is outputted from the output terminal Tout and when not, an inverting signal is outputted from the output terminal Tout. In the case of switching noninverting/inverting outputs, each of the analog switches 16, 18 is simultaneously and tentatively turned on. As a result, an output signal Sout is switched at a high speed in the noninvertingly or invertingly without causing distortion or noise.
Inventors:
Sei Yamamoto
Akitaka Murata
Akitaka Murata
Application Number:
JP24358596A
Publication Date:
April 26, 2006
Filing Date:
September 13, 1996
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H03L7/095; G01C19/56; G01C19/5776; H03D1/22; H03L7/085; H04L27/00; (IPC1-7): H03L7/095; H03D1/22; H04L27/00; //G01C19/56; G01P9/04
Domestic Patent References:
| JP5291945A | ||||
| JP6140840A | ||||
| JP3180788A |
Attorney, Agent or Firm:
Tsutomu Adachi
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