Title:
SYNCHRONIZATION MESSAGE TRANSMISSION DEVICE
Document Type and Number:
Japanese Patent JP3681225
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the stability of a synchronous network and guarantee the quality by incorporating information, indicating that a transmit frame can not be used as the master clock of an opposite station, in a message.
SOLUTION: This device is provided with a message comparison part 7 which supplies comparison information on the quality level of a clock to one of a message process part 2, a message insertion part 3, and a signal transmission part 4. Then the information indicates that the quality level of the clock prescribed in the message is lower than the quality level of an internal clock, one of the process part 2, insertion part 3, and signal transmission part 4 puts information, indicating that the transmit frame can not be used as the master clock of the opposite station, in a transmit synchronization message.
Inventors:
Yoshitaka Taki
Kazuhiko Hata
Junji Yamamoto
Kazuhiko Hata
Junji Yamamoto
Application Number:
JP20166796A
Publication Date:
August 10, 2005
Filing Date:
July 31, 1996
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04J3/00; H04J3/06; H04J3/14; H04J3/16; H04L7/00; H04M3/22; H04L1/20; (IPC1-7): H04J3/00; H04J3/14; H04L1/20; H04L7/00; H04M3/22
Domestic Patent References:
| JP7095677A | ||||
| JP8079211A | ||||
| JP7087047A | ||||
| JP3258046A | ||||
| JP4047823A | ||||
| JP7226729A | ||||
| JP7087117A | ||||
| JP7283803A | ||||
| JP3253129A | ||||
| JP7235918A |
Attorney, Agent or Firm:
Shuji Moizumi
Previous Patent: ENCLOSURE STRUCTURE OF ELECTRICAL EQUIPMENT DEVICE AND ITS DISASSEMBLY METHOD
Next Patent: POLISHING DEVICE AND METHOD
Next Patent: POLISHING DEVICE AND METHOD