PURPOSE: To prevent a synchronizing pattern from being detected in error by avoiding the synchronizing pattern from being inputted to a synchronism detection circuit except at the reception time.

CONSTITUTION: A gate circuit 11 is opened at a reception timing and a reception signal is inputted to a serial-parallel converting section 16 via an equalizer 12 and a unipolar/bipolar converting circuit 13. A reception timing signal is given to the converting section 16 and when this signal is given, a high-order bit of the output of the converting section 16 is inputted to the synchronism detection circuit 7. A frame synchronism signal being an output of the synchronism detection circuit 7 is given to a register 17 to read the parallel output.