Title:
SYNCHRONIZING CIRCUIT
Document Type and Number:
Japanese Patent JP2715953
Kind Code:
B2
Abstract:
PURPOSE: To omit frame and word double asynchronous discrimination to shorten the asynchronous detection time by directly outputting a frame asynchronous discrimination signal as an asynchronous detection signal.
CONSTITUTION: A reception data signal 11 where a frame is an integral number of times as long as the word length of the fundamental unit of error correction operation is inputted to an error correction operation circuit 1, a frame synchronizing circuit 3, and a frame asynchronous detection circuit 4 in parallel. The operation circuit 1 performs the error correction operation of the signal 11 to output a correction data signal 12 to the outside and generates a syndrome signal 13 to input it to a word synchronous circuit and performs word synchronous discrimination to generate a word synchronous discrimination signal 14. The frame synchronizing circuit 3 receives the signal 14 and compares frame synchronizing bits to generate a frame synchronous discrimination signal 15, and the frame asynchronous detection circuit 4 receives the signal 15 and counts the frequency in noncoincidence of frame synchronizing bits in the data signal 11 to output it as a frame asynchronous detection signal.
Inventors:
Akio Yamada
Application Number:
JP1645595A
Publication Date:
February 18, 1998
Filing Date:
January 06, 1995
Export Citation:
Assignee:
NEC
International Classes:
H04L1/00; H04J3/06; H04L7/08; (IPC1-7): H04L7/08; H04J3/06; H04L1/00
Domestic Patent References:
| JP5244142A |
Attorney, Agent or Firm:
Hachiman Yoshihiro
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