PURPOSE: To provide a synchronizing clock generation circuit which generates a reference clock signal that has high accuracy of synchronization and can deal with a wide range of frequency without increasing the circuit constitution.

CONSTITUTION: The delay element groups 110, 120 and 130 are successively connected to a reference clock input terminal 1 to construct a delay clock generation circuit 10a. An asynchronizing signal input terminal 2 is connected a storage/phase detection circuit 20a consisting of a storage circuit 200a and a phase detection circuit 300a. When the frequency of a reference clock is comparatively high, a delay clock having the comparatively small delay value is used. Meanwhile a delay clock having the comparatively large delay value is used when the frequency of the reference clock is comparatively low. Thus it is possible to generate a synchronizing clock which can deal with the reference clock having a wide range of frequency and therefore to obtain a synchronizing clock generation circuit that has a wide allowance range of frequency of the reference clock.