Title:
SYNCHRONIZING COUNTER
Document Type and Number:
Japanese Patent JPH05327480
Kind Code:
A
Abstract:
PURPOSE: To provide a synchronizing counter which eliminates the spike noises out of the ripple carry output and also attains a high speed operation.
CONSTITUTION: A 1st flip-flop circuits 2, 4, 6 and 8 are cascaded at plural stages, and a 2nd flip-flop circuit 10 is provided to the circuit 8 of the final stage. When the output of the circuit 2 of the first stage is kept at a low level with the output of the circuits 4-8 kept at a high level respectively, each output of circuits 2-8 defined as the data input of the circuit 10. Thus the carry output is obtained from the circuit 10.
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Inventors:
TSUTSUMI KUNIHIRO
Application Number:
JP15566392A
Publication Date:
December 10, 1993
Filing Date:
May 23, 1992
Export Citation:
Assignee:
ROHM CO LTD
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Shoichi Unemoto