PURPOSE: To reduce jitter due to the delay of detection of a vertical synchronizing signal by generating a clock signal at a timing by which an extracted synchronizing signal is delayed for micro time, reading the synchronizing signal extracted with the clock signal in a shift register, and detecting the vertical synchronizing signal from a pattern outputted from each stage of the shift register.

CONSTITUTION: The extracted synchronizing signal SY is inputted to a clock signal generation circuit 14. The clock signal generation circuit 14 is comprised of a timer circuit 16, and outputs the clock signal CK rising at a timing by which the trailing edge of an inputted synchronizing signal is delayed for prescribed time(for example, 13.5μs) and falling at the next trailing edge timing of the synchronizing signal SY, and the clock signal, the inverse of CK inverted from the signal CK. The shift register 18 is comprised of serial shift registers of eight constitution, and reads and shifts the extracted synchronizing signal SY at the leading edge timing of the clock signal, the inverse of CK sequentially. Each output of the stages QA-QG of the shift register 18 is inputted to a vertical synchronization detection circuit 25. The output of lower stages QA, QB, QC, and QD, after only the output of the first stage QA being inverted at an inverter 20, are inputted to an AND circuit 22, respectively.