To separately generate a clock synchronized with an MPU clock without needing any wirings for a high frequency signal on a circuit board and to generate various signals with the clock as a synchronizing signal.

A timing generation part 201 inputs FDCCLK 2 whose frequency is twice as much as SYSCLK that MPU 10 outputs from a transmitter 50, divides the frequency into two and generates four types of signals whose phases are deviated by 90 degrees. The signal with the smallest phase deviation with respect to the system clock SYSCLK is selected from them and a wait signal with respect to access to LCD is generated with the signal as a pseudo SYSCLK signal.