PURPOSE: To generate signals synchronized with many burst input signals, by constituting a digital phase lock circuit equipped with a storage circuit, which stores and holds phase information corresponding to the number of input burst signals, and a timing control circuit.

CONSTITUTION: The phase difference between a burst input signal 1a and an output phase signal 61a is detected by a phase detecting circuit 22 to generate an advance detectin signal 22a or a lag detection signal 22b. A digital low pass filter circuit 36 transmits an advance control signal 36a or a lag control signal 36b in accordance with the variation of signals 22a and 22b. A digital phase shift circuit 61 controls the phase of an output signal 61b in accordance with signals 36a and 36b and outputs an output phase signal 61a and a phase signal 61c. A storage circuit 9 is controlled by a timing contol circuit 81 to store a filter signal 36c and the phase signal shift circuit 61 as initial value signals 9a and 9b shift circuit 61 as initial value signals 9a and 9b.