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Patent Searching and Data


Title:
SYNCHRONIZING SIGNAL SEPARATING DEVICE
Document Type and Number:
Japanese Patent JPH04157983
Kind Code:
A
Abstract:

PURPOSE: To settle the synchronous state even in a strong ghost condition by obtaining a minimum peak value of the output of an integrating circuit by a peak holding circuit and comparing the minimum peak value and the output of the integrating circuit with each other by a comparing circuit and shaping the waveform of the comparison result.

CONSTITUTION: A comparing circuit 14 compares the output of an integrating circuit 13 with a reference voltage 17 to generate a mask signal indicating the vertical synchronizing period and gives this signal to a peak holding circuit 15. The circuit 15 holds the minimum peak value of the output of the circuit 13 in the period, when the mask signal is in the low level, and gives it to the comparing circuit 14. The output in the high level is outputted from a comparing circuit 16 if the output of the circuit 13 is larger than the peak hold output in the vertical synchronizing period, and the final rising edge of the peak hold output coincides with the end timing of the vertical synchronizing period. Further, a comparing circuit 19 shapes the waveform by comparison with a reference voltage to obtain the vertical synchronizing signal separation output in an output terminal 21.


Inventors:
MIYAZAKI ISAO
Application Number:
JP28497690A
Publication Date:
May 29, 1992
Filing Date:
October 22, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA AVE KK
International Classes:
H04N5/10; (IPC1-7): H04N5/10
Attorney, Agent or Firm:
Susumu Ito