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Patent Searching and Data


Title:
SYNCHRONIZING UP-DOWN COUNTER
Document Type and Number:
Japanese Patent JPH044611
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of circuit components and to simplify the wiring by providing a 1st control circuit changing the polarity of a counter output, a carry signal/borrow signal generating circuit, a 2nd control circuit changing the polarity of a counter output, and a register so as to obtain a counter output.

CONSTITUTION: Counter outputs Qa-Qc whose polarity is changed by an up-down control signal are obtained from 1st control circuits 15b-15d. A carry signal is outputted in the UP mode from carry signal/borrow signal generating circuits 17b-17d and a borrow signal is generated in the DOWN mode. Then the polarity of the counter outputs Qa-Qc is changed by a carry signal or a borrow signal in the 2nd control circuits 19a-19c to obtain a count value after one clock. Thus, a changeover circuit for a carry signal generating circuit and a borrow signal generating circuit is not required, the number of circuit components is reduced and the wiring is simplified.


Inventors:
SHIRAISHI MASARU
Application Number:
JP10684690A
Publication Date:
January 09, 1992
Filing Date:
April 23, 1990
Export Citation:
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Assignee:
SHARP KK
International Classes:
H03K23/86; (IPC1-7): H03K23/86
Attorney, Agent or Firm:
Kazuhide Okada