PURPOSE: To ensure the accurate operations of the latch circuits which are placed between both synchronous circuits.

CONSTITUTION: A 1st synchronous circuit 10 includes a 1st latch circuit 11 which generates a 1st output signal synchronously with a clock of a 1st phase. A delay circuit 40 is connected to the output terminal of the circuit 11 and generates a 2nd output signal by delaying the 1st output signal by a prescribed phase value. A 2nd synchronous circuit 20 includes a 2nd latch circuit 21 which inputs the 2nd output signal received from the circuit 40 and generates a 3rd output signal synchronously with the clock of the 1st phase and also with a clock of a 2nd phase different from the 2nd output signal.