To provide a synchronous correction circuit capable of preventing synchronous correction to reflected waves.

The synchronous correction circuit 10 loads data 34 supplied to a bit counter 16, according to the presence or absence of an UW detection signal 26 from an UW detection circuit 12 within a range value indicated by an enable signal 30 from a synchronous correction 20 in a load generation circuit, thus excluding the UW detection signal 26 detected, since it deviates by a large amount to perform synchronous correction, and enabling the synchronous correction, based on normal reception wave, without picking up signal waves assumed to be the reflected wave.