PURPOSE: To improve the available highest frequency by latching each output signal from a ripple down-counter with a counter output at a lower-order by required bits.

CONSTITUTION: A most significant bit output QN from an asynchronous ripple down-counter 1 is latched by a 1st stage D FF latch circuit 2-1 based on an output QN-2 lower by two bits, and latched by a circuit 2-2 based on an output QN-3 lower by one bit than the output QN-2. The similar operation is executed by latch circuits 2-1-2-(N-2), an UP output is outputted from a final stage latch circuit 2-(N-1) and the entire circuit acts like a synchronous UP counter. Through the constitution above, a delay time by one stage of the FF being a component of the counter circuit is remarkably smaller than that of plural D FFs, exclusive OR circuits or OR circuits operated at the edge of the same clock and the available highest frequency is enhanced.