Title:
SYNCHRONOUS COUNTER AND ITS METHOD OF USE
Document Type and Number:
Japanese Patent JPH05175831
Kind Code:
A
Abstract:
PURPOSE: To provide a high-speed counter having a high operating frequency and the method of use.
CONSTITUTION: In the synchronous counter where flip flops FF0 to FF3 whose number corresponds to the number of bits and the same number of AND gates A0 to A3 as these flip flops are provided and AND gates A0 to A3 form a series carry line, D flip flops DF0 and DF1 are inserted in series to the series carry line of AND gates A0 to A3 at intervals of m bits ((m) is a positive integer). Since D flip flops DF0 and DF1 are inserted at intervals of m bits, the propagation distance of the intermediate result is shortened, and therefore, the high-speed counter having a high operating frequency is provided.
Inventors:
NAKAMURA SHINJI
AKUTAGAWA KIYOSHI
ABE NORIYUKI
AKUTAGAWA KIYOSHI
ABE NORIYUKI
Application Number:
JP33899591A
Publication Date:
July 13, 1993
Filing Date:
December 20, 1991
Export Citation:
Assignee:
NISSAN MOTOR
International Classes:
H03K23/40; (IPC1-7): H03K23/40
Attorney, Agent or Firm:
Junnosuke Nakamura (1 outside)