PURPOSE: To count plural bits at a high speed.
CONSTITUTION: First and second synchronous counter circuits 10a, 10b adopt circuit configuration similar to that of conventional counters and a bit number handled by the synchronous counters is halved. Moreover, a carry signal C generated by an AND gate 20 on the occurrence of carry of the 1st synchronous counter circuit 10a is inputted to the 2nd synchronous counter circuit 10b. A fan-out of a JK-FF1-1 outputting an LSB signal in the synchronous counter circuit 10a is (m-1). Furthermore, a fun-in of the AND gate 20 connecting to inputs J, K of a JK-FF1-8 outputting an MSB signal in the synchronous counter circuit 10b is (n-1). Thus, the fan-out and the fan-in are less than those of a conventional synchronous counter thereby enhancing the operating speed when plural bit numbers are processed.
| JPH04503135 | [Title of the Invention] High-speed prescaler |
| WO/2004/105247 | VARIABLE DIVISION METHOD AND VARIABLE DIVIDER |
NEMOTO MASAHISA
SEKI SHOHEI
