Title:
SYNCHRONOUS DRAM
Document Type and Number:
Japanese Patent JP3881565
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a synchronous DRAM of which read speed of data is improved.
SOLUTION: This synchronous DRAM has a first common data line connected to a transfer circuit of the first and the third memory cell blocks and transfers data read out from one side of the memory cell blocks, a second common data line connected to a transfer circuit of the second and the fourth memory cell blocks and transfers data read from one side of the memory cell blocks when data is read from the memory blocks of the first and the third memory blocks, and an output circuit connected to the first and the second common data lines, outputting data on the first common data line in response to rise of a clock signal, and outputting data on the second common data line in response to fall of a clock signal.
Inventors:
Takashi Ohno
Hitoshi Doi
Hitoshi Doi
Application Number:
JP2002053417A
Publication Date:
February 14, 2007
Filing Date:
January 28, 1999
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G11C11/409; G11C11/401; G11C11/407; (IPC1-7): G11C11/409; G11C11/401; G11C11/407
Domestic Patent References:
| JP10334663A | ||||
| JP9289293A |
Attorney, Agent or Firm:
Koichi Suzuki
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