Title:
SYNCHRONOUS DRAM
Document Type and Number:
Japanese Patent JPH07262772
Kind Code:
A
Abstract:
PURPOSE: To immediately start the self-refreshing operation and to increase the operating speed when self-refreshing instruction is inputted in an SDRAM operated in synchronization with a clock signal (a system clock signal) supplied from the outside.
CONSTITUTION: When self-refreshing instruction is fetched, a selfrefreshing signal SR in a first cycle is outputted in synchronization with the rising edge of the oscillation output of an oscillator circuit 25. The self-refreshing signal SR after a second cycle is outputted in synchronization with the rising edge of the frequency-divided output of a frequency divider 26.
Inventors:
ENDO TETSUYA
Application Number:
JP4702494A
Publication Date:
October 13, 1995
Filing Date:
March 17, 1994
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G11C11/403; G11C11/407; (IPC1-7): G11C11/403
Attorney, Agent or Firm:
Tetsuo Hirado
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