To accelerate data transfer by providing a first switching element transferring the data or a command from an input terminal to a command decoder in synchronism with a reference clock and a second switching element transferring the decoded data or command to an internal circuit.

The data or the commands A, B, C from the outside are inputted to the first switching elements Q11-13 turning ON/OFF in synchronism with the rise/fall of the reference clock CLK and the command decoder CD through input buffers B11-13 to be decoded. The decoded data or commands A, B, C are transferred to the internal circuit through the second switching elements Q14-16 turning ON/0FF in synchronism with the rise/fall of the reference clock CLK. Thus, the data transfer in a synchronous DRAM is accelerated.