PURPOSE: To suppress consecutive information bit 0s at input interruption by supervising N-set of inputted staff signals and using a special pattern in case of the input interruption to apply synchronism multiplexing.

CONSTITUTION: Staff synchronism circuits 7, 8, 9 input respectively two low- order group signals, generate staff synchronizing signals A, B, C subjected to duplicatedly multiplexing and input them to input interruption detecting circuits 15, 16 and 17 in synchronization with a clock dividing a click from a high-order group clock generator 10 into 1/3 by a 1/3 frequency divider circuit 11. The circuits 15, 16, 17 supervise respectively the input of the signals A, B, C give an output to a synchronism multiplexing circuit 12 as it is when an input exists, and when the input interruption is detected, and special pattern from a special pattern generating circuit 14 is outputted to the circuit 12 in place of the input staff synchronizing signal immediately. The form of the special pattern signal is decided so as to decrease information bits 0 as less as possible. Thus, when the staff synchronism signal is interrupted, the consecutive 0s are suppressed and the clock is extracted easily by the reception side.