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Title:
SYNCHRONOUS MULTIPLEX TRANSMITTER
Document Type and Number:
Japanese Patent JP2000101538
Kind Code:
A
Abstract:

To provide a synchronous multiplex transmitter capable of removing the slip in frame synchronization due to the frequency deviation of an intra-system master clock generated and outputted from the terminating devices of respective systems by respectively attaining frame synchronization in the synchronous multiplex transmitter within the same system and between the plural systems.

A master clock S1 for inter-system synchronization and frame synchronizing signals S2 for the inter-system synchronization generated and outputted from a synchronizing signal generator 4 are transmitted to the controllers 1 and 11 of the respective systems A1 and A2. In the controllers 1 and 11, reset signals S4 for synchronization are imparted to outgoing data S3 with the master clock S1 for the inter-system synchronization and the frame synchronizing signal S2 for the inter-system synchronization as reference and they are transmitted to the terminal devices 2 and 12 of the respective systems Al and A2. Intra-system frame synchronizing signals S12 are detected in the terminal devices 2 and 12 and respectively transmitted to the controllers 1 and 11 of the respective systems A1 and A2 and terminals 3a, 3b,...3n and 13a, 13b,...13n and thus, the frame synchronization is attained within the same system and between the plural systems.


Inventors:
KATO ISAO
Application Number:
JP27108898A
Publication Date:
April 07, 2000
Filing Date:
September 25, 1998
Export Citation:
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Assignee:
AIPHONE CO LTD
International Classes:
H04J3/06; H04L12/40; (IPC1-7): H04J3/06; H04L12/40
Attorney, Agent or Firm:
Moriya Kazuo