Title:
SYNCHRONOUS PULL-IN METHOD FOR PLL CIRCUIT
Document Type and Number:
Japanese Patent JP3148182
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make the phase adjustment of a clock in a wide range and to stabilize the operation by turning a voltage range in the synchronous state of a circuit to a dead zone and constituting a VCO sweep circuit operated for the positive and negative bidirectional deviation of a VCO drive voltage accompanying with pull-out.
SOLUTION: A VCO sweep circuit for performing pull-in is constituted of Q21-Q24 and R24-R33, etc. When pull-out occurs, the output potential of an error amplifier 20 becomes high and the Q22 is turned on, the output current of the amplifier 20 is inputted through the R25 or the like to a negative input terminal, forms a negative feedback loop and performs the action of canceling an offset voltage applied by VR21 and R22. Also, when the output potential of the amplifier 20 becomes low by the pull-out, the Q21 is turned on, the Q23 and Q24 are turned on in linkage and the collector current of the Q24 is supplied from a VREF through the R30 or the like, lowers the negative input terminal voltage of the amplifier 20, acts in the direction of making the potential of an output terminal positive, forms the negative feedback loop and cancels the offset voltage.
Inventors:
Suguru Kamura
Application Number:
JP21468498A
Publication Date:
March 19, 2001
Filing Date:
July 30, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H03L7/093; H03L7/10; H03L7/12; (IPC1-7): H03L7/12
Domestic Patent References:
| JP59210731A | ||||
| JP5300398A |
Attorney, Agent or Firm:
Yoshihiro Morimoto