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Patent Searching and Data


Title:
SYNCHRONOUS REGENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPS63132533
Kind Code:
A
Abstract:

PURPOSE: To prevent noises and jitters from appearing in a synchronous reproduction output by extracting a clock from only a data input signal when a binary signal indicates a light input above a specific level and feeding the output of a clock extraction part back to an input side when below the specific level.

CONSTITUTION: When the light input from an optical fiber cable exceeds the specific level, the output of a full-wave rectifying circuit 3 and the input of a resonance circuit 4 are connected electrically and the output of a feedback circuit 6 and the resonance circuit 4 are disconnected electrically. A differential pulse corresponding to a data input signal is generated by a differentiating circuit 2 and supplied to the resonance circuit 4. Consequently, a clock extraction part 10 extracts a timing clock having no jitters without being affected by the feedback circuit 6. When the light input does not exceeds the specific level, the output terminal of the feedback circuit 6 is connected electrically to the input terminal of the resonance circuit 4 and the output terminal of the full-wave rectifying circuit 3 and the input terminal of the resonance circuit are disconnected.


Inventors:
MATSUSHITA TADASHI
Application Number:
JP27947386A
Publication Date:
June 04, 1988
Filing Date:
November 21, 1986
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H04B10/60; H04B7/02; H04B10/07; H04B10/2507; H04B10/40; H04B10/50; H04B10/69; H04L7/027; H04L25/40; (IPC1-7): H04B7/02; H04B9/00; H04L25/40
Attorney, Agent or Firm:
Yoshiki Hasegawa