Title:
SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3951202
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce current dissipation of a DQM buffer by enabling the DQM input buffer only when any one of the low active signal, first CAS waiting time signal and a signal of logical AND between the waiting time signal and second CAS waiting time signal is active and by disabling such DQM input buffer in other cases.
SOLUTION: During the refresh mode, a refresh signal RFS is set in the active condition of logical high level and an output signal PDQM is set to inactive condition. When the power is off, a power-down signal PWD is set to high level and the output PDQM is set to inactive condition. During the condition that both refresh signal RFS and lower-down signal PWD are in the low level, he DQM input buffer 21 is in the enable condition only when any one of the low active signal PRAL, first CAS waiting time signal CLI and signal LAC as the logical AND of the waiting time signal LATENCY2 and second CAS waiting time signal CL4 is in the active condition.
Inventors:
Chung Matan
Bae Toru
Bae Toru
Application Number:
JP7452698A
Publication Date:
August 01, 2007
Filing Date:
March 23, 1998
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/407; G11C11/409; G11C7/00; G11C7/10; G11C11/4076; G11C11/4093; (IPC1-7): G11C11/407; G11C11/409
Domestic Patent References:
| JP9046207A | ||||
| JP9167485A | ||||
| JP7177015A | ||||
| JP6195963A | ||||
| JP1118292A | ||||
| JP9027192A | ||||
| JP7230688A | ||||
| JP6203563A | ||||
| JP7045067A | ||||
| JP9106682A | ||||
| JP2000074952A |
Attorney, Agent or Firm:
Yasunori Otsuka
Kenichi Matsumoto
Kenichi Matsumoto
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