Title:
同期型半導体記憶装置
Document Type and Number:
Japanese Patent JP4141520
Kind Code:
B2
Abstract:
A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped.
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| JP5795486 | Data input circuit |
Inventors:
Mikio Sakurai
Yata Susumu
Yasuhiko Tsukikawa
Zenya Nakano
Takahiko Fukigami
Yata Susumu
Yasuhiko Tsukikawa
Zenya Nakano
Takahiko Fukigami
Application Number:
JP31373997A
Publication Date:
August 27, 2008
Filing Date:
November 14, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C11/407; G01R31/317; G11C11/401; G11C11/4072; G11C29/14
Domestic Patent References:
| JP5242698A | ||||
| JP9106668A | ||||
| JP9259582A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai