PURPOSE: To attain a test in a device single body, to simplify a scan test, to effectively utilize the whole LSI chip and to increase its integration degree by providing a selector and a register on each stage of a register part.

CONSTITUTION: This device is provided with plural stages of register parts provided corresponding to respective columns of a memory cell array 1, and the register part of each stage is provided with the selectors 12x-12o and the registers 13x-13o, and each register constitutes a scan chain through the selector. The selectors 12x-12o select either one of the input data Ix-Io, the output data TAx-TAo at the time of a test mode or the scan input data SIx-SIo based on internal control signals a-c. The registers 13x-13o latch the selected data in response to an internal clock signal CKM*, CKS*. Thus, when a scan mode is moved to the test mode, the data are written in a memory cell corresponding to an optional column by using an asynchronous write signal LD.