Title:
同期式順序回路のプロパティ検証方法および装置
Document Type and Number:
Japanese Patent JP4577475
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To solve the problems that verification can not be performed when processing is restricted and that a logic circuit being equal to or larger than a prescribed scale can not be verified when there are limitations in a processing memory and processing CPU time. SOLUTION: A property verifying method for verifying whether a synchronous sequential circuit satisfies function specifications is provided with a step for inputting a description that defines the operation of the synchronous sequential circuit and function specifications of the synchronous sequential circuit, a step for performing property verification by a symbol model examination method, a step for generating a test bench by using information utilizing the results of the symbol model examination method in the case the property verification by the symbol model examination method cannot be performed within limited time or limited memory quantity, and a step for using the test bench to perform logic simulation for complementing the results of the symbol model examination method.
Inventors:
Teru Mukaiyama
Application Number:
JP2001219343A
Publication Date:
November 10, 2010
Filing Date:
July 19, 2001
Export Citation:
Assignee:
NEC
International Classes:
G06F17/50
Domestic Patent References:
| JP2000181939A | ||||
| JP6208601A | ||||
| JP2000305977A | ||||
| JP2002099584A |
Attorney, Agent or Firm:
Jyohei Yamashita
Michio Nagai
Jyohei Yamashita
Michio Nagai
Jyohei Yamashita