PURPOSE: To obtain this device having a small circuit scale by providing a computing element by which data outputted from memory is multiplied by 1 or a, a2-am-1 corresponding to address input, and a DFF to latch the output of the element for clock input.

CONSTITUTION: A value Dn-1 as parallel data (a) is inputted, and the clock input (c) inputs four clocks. The memory 103 outputs a value Dn when an address input value shows zero, and a selector 111 selects and outputs the Dn. The DFF 112 latches and outputs the output Dn of the selector 111 at the rise of the input (c). The value Dn-1 of the data (a) and the output Dn of the DFF 112 are inputted to an adder 101, and a value (Dn+Dn-1) is outputted as a result, and is stored in the address 0 of the memory 103 at the timing of the rise of the input (c). The same operation is repeated on address input values 1-3, and S0-S3 are stored in the addresses 0-3 of the memory 3 after a value D1 is inputted as the data (a). When the address input 0-3 are supplied by setting the input (c) at H, S0-S3 can be obtained from output 109.