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Title:
SYNTHESIZER AND SIGNAL ANALYZER
Document Type and Number:
Japanese Patent JP3773250
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a synthesizer and a signal analyzer which perform edge arrangement of exact and high resolution without necessity of system clock of frequency very higher than frequency of a synthetic clock signal. SOLUTION: It comprises a system clock signal source for a system clock signal; a phase data resource for a phase data signal; an interpolater, coupled to the phase data source, which receives a system phase data signal to synchronize with a clock signal, answers every received phase data signal, and generates a contiguous edge arrangement data signal; and a phase modulator, coupled to this interpolater, which generates a clock output signal with an edge arranged at the point determined by series edge arrangement data signal.

Inventors:
Dan Etch Wallever
Daniel G. Nielim
Application Number:
JP2004123490A
Publication Date:
May 10, 2006
Filing Date:
April 19, 2004
Export Citation:
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Assignee:
TEKTRONIX,INC.
International Classes:
H03K5/15; H03L7/00; H03K5/1532; H03K21/00; (IPC1-7): H03L7/00; H03K5/15; H03K5/1532; H03K21/00
Domestic Patent References:
JP5037311A
JP62198771A
JP10153626A
Attorney, Agent or Firm:
Kunio Yamaguchi
Eiji Sasaki



 
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