PURPOSE: To reduce the size and cost of a system clock generator capable of temporarily changing the frequency of a clock and increasing or decreasing the number of clocks to be generated within a certain period.

CONSTITUTION: An input clock is frequency-divided by a variable frequency divider 2 and the frequency-divided clock is inputted to a PLL circuit 3. The frequency dividing ratio of the frequency divider 2 is controlled by a frequency dividing ratio control circuit 1, and when a control signal is inputted from the external, the frequency dividing ratio of the divider 2 is changed only for a certain fixed period. An output clock is extracted from the PLL 3, and when a control signal is not inputted from the external, the phase of the output clock is synchronized with that of the input clock.