PURPOSE: To improve a processing speed by merging a store instruction and executing it as one store operation when the store instruction successively appears to the memory of the same bank.
CONSTITUTION: A store address is converted to a real address and stored to a store buffer register 4. The contents of the store buffer register 4 are compared by an address comparing circuit 5 and when they are access to the same bank, it is informed a merge circuit 10. On the other hand, store data are continuously stored to a store data buffer 8. A bite mark is continuously stored through a bite mark register 11 to a store bite mark buffer 12 in the same way. When the access to the same bank is obtained, those data are merged by a merge circuit 10 and the bite mark is merged by a merge circuit 13. Then, they are stored to the memory at a time.
JPS6238953A | 1987-02-19 |