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Patent Searching and Data


Title:
SYSTEM FOR CONTROLLING STORE BUFFER
Document Type and Number:
Japanese Patent JPS6431238
Kind Code:
A
Abstract:

PURPOSE: To improve a processing speed by merging a store instruction and executing it as one store operation when the store instruction successively appears to the memory of the same bank.

CONSTITUTION: A store address is converted to a real address and stored to a store buffer register 4. The contents of the store buffer register 4 are compared by an address comparing circuit 5 and when they are access to the same bank, it is informed a merge circuit 10. On the other hand, store data are continuously stored to a store data buffer 8. A bite mark is continuously stored through a bite mark register 11 to a store bite mark buffer 12 in the same way. When the access to the same bank is obtained, those data are merged by a merge circuit 10 and the bite mark is merged by a merge circuit 13. Then, they are stored to the memory at a time.


Inventors:
NOZAWA KEIZO
Application Number:
JP18693587A
Publication Date:
February 01, 1989
Filing Date:
July 27, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/08; G06F12/00; G06F12/04; G06F12/06; (IPC1-7): G06F12/00; G06F12/08
Domestic Patent References:
JPS6238953A1987-02-19
Attorney, Agent or Firm:
Takashi Honma