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Title:
SYSTEM AND EQUIPMENT FOR SERIES-PARALLEL CONVERTING TRANSMISSION
Document Type and Number:
Japanese Patent JPH06311197
Kind Code:
A
Abstract:

PURPOSE: To solve the problem of stability, cost and power consumption by suppressing circuits operating at every high speed to be minimum by outputting each channel signal to a prescribed channel by letting a transmission side add a synchronization code and an ID code and letting a reception side discriminate an ID code.

CONSTITUTION: In a transmission part, two channels of data D1 and D2 are inputted from input terminals 1 and 2 and synchronization code adding circuits 3 and 4 add synchronization code common to each channel. Besides, channel ID adding circuits 5 and 6 add ID codes different at every channel. A parallel- serial conversion circuit 9 converts the two pieces of added data 7 and 8 to one piece of two-channel multiplexed serial data of a high bit rate and an interface 11 output it. In a reception part, a reception interface circuit 13 receives data 12 transmitted by way of the transmission circuit to reproduce serial data corresponding to data 10. The piece of data is converted into the two channels of the signals 16 and 17 of low bit rates by a serial-parallel conversion circuit 15 and outputted by way of a switching circuit 18.


Inventors:
MORI YASUSHI
MURATA NORIO
Application Number:
JP13979993A
Publication Date:
November 04, 1994
Filing Date:
April 23, 1993
Export Citation:
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Assignee:
HITACHI ELECTRONICS
International Classes:
H03M9/00; H04L69/14; (IPC1-7): H04L29/04; H03M9/00