Title:
SYSTEM FOR INSPECTING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004177160
Kind Code:
A
Abstract:
To solve the problem that expensive facilities have been required for raising the number of devices for simultaneous inspection and that it has been difficult to perform different inspections device by device.
A plurality of devices (DUTs) 101-104 to be measured are serially connected to an inspection device (memory tester) 105. Assigned identifiers (DUT number/ID number) are each previously allotted to the DUTs 101-104. Each of the DUTs 101-104 is provided with a comparison circuit 201 for comparing transmission identifiers (DUT number/ID number) by the memory tester 105 each with the individual assigned identifiers of the DUTs 101-104 and activating inspection only when matched.
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Inventors:
KURAKI TOSHIO
Application Number:
JP2002340751A
Publication Date:
June 24, 2004
Filing Date:
November 25, 2002
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Kazuhide Okada
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