To achieve a system memory control device for connecting a control signal and an address signal through a common bus.

This system memory control device includes: a command synchronization device 14 for generating CME-0 and CME-1 which are made exclusively valid; a unit system memory control device 13a for generating CS-0, CTL-0 and AD-0 based on CME-0 and ACQ-0 from a data processor 16, and for outputting CTL-0 and AD-0 synchronously with CS-0; a unit system memory control device 13b for generating CS-1, CTL-1 and AD-1 based on CME-1 and ACQ-1 from the data processor 16, and for outputting CTL-1 and AD-1 synchronously with the CS-1; and a command selection device 15 for selecting CTL-0 and AD-0 or CTL-1 and AD-1, and for outputting it through a common bus to system memories 11a and 11b.