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Title:
SYSTEM AND METHOD FOR DELAYING EXCEPTION GENERATED DURING SPECULATIVE EXECUTION
Document Type and Number:
Japanese Patent JP2000112758
Kind Code:
A
Abstract:

To provide a method for supporting the speculative execution of an instruction set.

The method is provided with a step (64) for evaluating the instructions of the instruction set during execution to judge whether the individual instruction is speculative or not, a step (70) for evaluating each of the speculative instructions to judge whether it generates an exception and a step (74) for encoding a deferred exception token(DET) to an unused register value of the register of CPU concerning each speculative instruction generating an exception. This system is provided with a circuit for evaluating the instruction of the instruction set to judge whether the individual instruction is speculative or not, a circuit for evaluating each of the speculative instructions to judge whether it generates an exception and a circuit encoding DET to the unused register value of the register of CPU in response to an assessing means.


Inventors:
GAUTAM B DOSHI
PETER MARKSTEIN
KARP ALAN H
JEROME C HACK
GLENN T COLON-BONNET
MICHAEL MORRISON
Application Number:
JP26702299A
Publication Date:
April 21, 2000
Filing Date:
September 21, 1999
Export Citation:
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Assignee:
HEWLETT PACKARD CO
International Classes:
G06F9/38; G06F9/45; G06F9/46; G06F9/48; (IPC1-7): G06F9/38; G06F9/38; G06F9/46
Attorney, Agent or Firm:
Tsukio Okada