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Patent Searching and Data


Title:
SYSTEM AND METHOD FOR LOGIC VERIFICATION
Document Type and Number:
Japanese Patent JP2002117094
Kind Code:
A
Abstract:

To provide a system and a method for logic verification which system and method each handles macros as a black box and can realize error detection and counting of the data variation rate between the macros by using only input and output data.

A test benchmark 100 has a means which inputs the input data 112 to a circuit 101 having macros 12x (x=1, 2...n) divided for each function, a means which monitors the input of data to the macros 12x (x=1, 2...n), and a means which decide whether or not the output data from the macros 12x (x=1, 2...n) corresponding to the input data 112 satisfy the specifications of the circuit 101 by using error detection parts 14x (x=1, 2...n) and specifies where in the circuit 101 a macro 12x having a bug is present when the circuit 101 has the bug.


Inventors:
ITO TAKAYUKI
Application Number:
JP2000307142A
Publication Date:
April 19, 2002
Filing Date:
October 06, 2000
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F17/50; G01R31/28; (IPC1-7): G06F17/50; G01R31/28
Attorney, Agent or Firm:
Jo Hori