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Title:
SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION
Document Type and Number:
Japanese Patent JP2007215213
Kind Code:
A
Abstract:

To provide a method for multiple-phase clock generation.

In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired number of clock phase outputs. The clock divider (304) in this embodiment includes a state machine, e.g., a modified Johnson counter (316), that provides a plurality of divided down clock phases, each of which is connected to separate modified shift registers (306-314). Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment, the number of clock phase outputs of the multiple-phase clock is a function which multiplies the number of VCO clock phases by the number of desired states in the modified Johnson counter.

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
KIM OOK
LI HUNG SUNG
LEE INYEOL
KIM GYUDONG
LEE YONGMAN
Application Number:
JP2007065275A
Publication Date:
August 23, 2007
Filing Date:
March 14, 2007
Export Citation:
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Assignee:
SILICON IMAGE INC
International Classes:
H03K5/15; G06F1/06; H03K21/00; H03K23/00; H03K23/54; H03L7/099; H03L7/089
Attorney, Agent or Firm:
古谷 聡
溝部 孝彦