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Patent Searching and Data


Title:
SYSTEM AND METHOD FOR PACKAGING ELECTRONIC DEVICES
Document Type and Number:
Japanese Patent JP2015122513
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method for packaging electronic devices which reduces a risk of blow-outs of melted solder without requiring masking materials, lithography or steps of removing excess solder.SOLUTION: The method includes melting solder for a solder jet 160. The method additionally includes depositing melted solder drops 130a from the solder jet 160 in a pattern on a first substrate 105a of a first component of an electronic device. The pattern comprises a plurality of individual dots 130b of melted solder. The method also includes aligning a second substrate 107 of a second component of the electronic device with the pattern deposited on the first substrate of the electronic device. The method further includes re-melting the solder deposited in the pattern on the first substrate. The method additionally includes, while the solder is re-melting, compressing the first and second substrates.

Inventors:
BUU DIEP
Application Number:
JP2015004979A
Publication Date:
July 02, 2015
Filing Date:
January 14, 2015
Export Citation:
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Assignee:
RAYTHEON CO
International Classes:
B23K1/00; H01L23/02; B23K3/06; B23K31/02; B23K35/30; C22C5/02
Domestic Patent References:
JP2009506565A2009-02-12
JP2003188294A2003-07-04
JP2008311429A2008-12-25
JP2010534948A2010-11-11
JP2007067400A2007-03-15
JP2009180682A2009-08-13
JP2009506565A2009-02-12
JP2003188294A2003-07-04
JP2008311429A2008-12-25
JP2010534948A2010-11-11
Foreign References:
US6566170B12003-05-20
US20100006336A12010-01-14
US20080110013A12008-05-15
WO2008140033A12008-11-20
US6566170B12003-05-20
US20100006336A12010-01-14
US20080110013A12008-05-15
Attorney, Agent or Firm:
Shinjiro Ono
Yasushi Kobayashi
Shigeo Takeuchi
Osamu Yamamoto
Shigeru Sakuma