To provide a system for designing/manufacturing a semiconductor package in which work load or work allotment is rationalized on the design side and the manufacturing side, and efficient design and manufacture are attained while shortening the time and reducing the cost.

Bonding data such as profile type and loop parameters created by a process engineer is transmitted to a CAD system 20 where wire clearance inspection is performed using the bonding data. The data after wire clearance inspection is transmitted to a wire bonder 40 or a virtual wire bonder control means 60, capillary locus coordinate data is created by the wire bonder control means 42 or the virtual wire bonder control means 60 of the wire bonder 40 and transmitted or outputted to the CAD system 20 where capillary interference inspection is performed using the capillary locus coordinate data.