To achieve system switching by maintaining the sequence of control signals thereby matching the inside data of both processors of active system/reserve system, and preventing the missing of the control signal in switching those systems, and securing inter-system synchronization.

When receiving a system switching request from an O&M controller 1, a host controller 21 does not perform instantaneous switching of a processor at a transmission destination from the active system 22 to the reserve system 23 but performs instantaneous switching only when any reply signal stand-by from an old active system is absent in a reply signal stand-by queue 215, and suppresses the transmission of the any new control signal to a processor until any reply comes when the reply signal stand-by is present in the reply signal stand-by queue 215. When any reply stand-by becomes absent in the reply signal stand-by queue 215, the host controller 21 transmits the suppressed control message to a new active system. Thus, it is possible to maintain the order of the control signal, and to secure the synchronization of the systems for achieving system switching.

COPYRIGHT: (C)2008,JPO&INPIT