PURPOSE: To facilitate the test of a decoder by cascading one input of an exclusive logic circuit so as to become the output of a delaying circuit, so that the result of decoding is propagated to a comparator, while being delayed at every clock.

CONSTITUTION: When a reset signal 11 is varied from '0' to '1', an initializing signal generating circuit 14 generates a test initializing signal 10 for1 clock, and initializes a testing circuit. Also, a multiplexer 7 receives the reset signal 11, and outputs it to a microcode bus 8 only for one clock. Therefore, one piece of microcode decoding outputs 50∼55 becomes '1'. In this case, in exclusive ORs 30∼35, the output of only the OR whose decoding output become '1' goes to '1'. This '1' is propagated to the next stage at every clock. A down-counter 3 is brought to -1 in response to a clock , therefore, an FF 13 is reset at the output time point of the last stage delay circuit 40. When the output of the object recorder does not go to '1', the FF 13 is set and abnormality is stored. A signal for deciding whether it is satisfactory or not is outputted from an output terminal 15.