半導体ウェーハの制御された研磨及びプレーナ化のためのシステム及び方法

Title:

半導体ウェーハの制御された研磨及びプレーナ化のためのシステム及び方法

Document Type and Number:

Japanese Patent JP4831910

Kind Code:

B2

Abstract:

A system and method for polishing semiconductor wafers includes a rotatable polishing pad movably positionable in a plurality of partially overlapping configurations with respect to a semiconductor wafer. A pad dressing assembly positioned coplanar, and adjacent, to the wafer provides in-situ pad conditioning to a portion of the polishing pad not in contact with the wafer. The method includes the step of radially moving the polishing pad with respect to the wafer.

More Like This:

WO/2015/122465	ADHESIVE FILM FOR PROTECTING SURFACE OF SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER PROTECTION METHOD USING ADHESIVE FILM
JP2010087116	SUBSTRATE PROCESSING APPARATUS
JPH1126421	PROCESSING METHOD OF SEMICONDUCTOR WAFER

Inventors:

Kistler rod
Gotokis Yeheal

Application Number:

JP2001554832A

Publication Date:

December 07, 2011

Filing Date:

January 12, 2001

Export Citation:

Click for automatic bibliography generation Help

Assignee:

APPLIED MATERIALS,INCORPORATED

International Classes:

H01L21/304; B24B37/26; B24B49/04; B24B51/00; B24B53/007; B24B53/017

Domestic Patent References:

JP2000015557A	2000-01-18
JPH10230450A	1998-09-02
JPH10551A	1998-01-06
JPH11204469A	1999-07-30
JPH05318325A	1993-12-03
JPH0929635A	1997-02-04
JPH09186118A	1997-07-15

Foreign References:

US5632873A	1997-05-27
WO1998015384A1	1998-04-16

Attorney, Agent or Firm:

Sonoda Yoshitaka
Kobayashi Yoshinori
Ikeda adult

Previous Patent: JPS4831909

Next Patent: コーティングされたスペーサを備えるフラットパネルディスプレイ装置