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Title:
TAPING METHOD OF SEMICONDUCTOR LEAD FRAME
Document Type and Number:
Japanese Patent JPH02106061
Kind Code:
A
Abstract:

PURPOSE: To prevent short circuit between wires and between a wire and a die pad by connecting the die pad periphery of a lead frame and the tip of an inner lead by using adhesive agent spread on the rear of a film.

CONSTITUTION: Adhesive agent is spread on the rear of a film 1. The film 1 is bonded and fixed in the manner in which the peripheral part of a die pad 21 of a lead frame (a) and the tip of an inner lead 20 are connected by adhesive agent 2. A rectangular window hole 1' is arranged at the central part of the film 1. The upper surface of the die pad 21 is exposed from the window hole 1' when the film 1 is bonded to the die pad 21. After a semiconductor chip 30 is die-bonded on the upper surface of the die pad 21 of the lead frame (a), exposed from the window hole 1', an electrode 31 of the semiconductor chip 30 and the inner lead 20 of the semiconductor lead frame (a) are connected by a wire 22. Thereby, short circuit between wires and between a wire and the die pad can be prevented.


Inventors:
FUSE MASAHIRO
KISANUKI HAJIME
Application Number:
JP1988000259115
Publication Date:
April 18, 1990
Filing Date:
October 14, 1988
Export Citation:
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Assignee:
DAINIPPON PRINTING CO LTD
International Classes:
H01L21/60; H01L23/50; (IPC1-7): H01L21/60; H01L23/50



 
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