Title:
自己選択メモリデバイスにアクセスするための技術
Document Type and Number:
Japanese Patent JP7027546
Kind Code:
B2
Abstract:
Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
Inventors:
Tortorelli, Innochenzo
Andrea Redaelli
Pirovano, Agostino
Pelitzer, Fabio
Allegra, Mario
Fantini, Paolo
Andrea Redaelli
Pirovano, Agostino
Pelitzer, Fabio
Allegra, Mario
Fantini, Paolo
Application Number:
JP2020531715A
Publication Date:
March 01, 2022
Filing Date:
November 29, 2018
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
G11C11/56; G11C13/00; H01L21/8239; H01L27/105
Domestic Patent References:
| JP2009534835A | ||||
| JP200512186A | ||||
| JP2006221737A | ||||
| JP200954274A |
Foreign References:
| WO2017078988A1 | ||||
| WO2018080615A1 |
Attorney, Agent or Firm:
Hiroyoshi Aoki
Masayuki Amada
Yoshiyuki Osuge
Yasuhisa Nomura
Masayuki Amada
Yoshiyuki Osuge
Yasuhisa Nomura