Title:
TEIDENJINO IC MEMORIIHOJIKAIRO
Document Type and Number:
Japanese Patent JPS5199418
Kind Code:
A
Abstract:
Memory device including an input circuit adapted to provide signal pulses to be applied to an IC counter so that they are counted by the counter. Auxiliary power source is provided to supply the power circuit in the counter to maintain the memory therein despite interruption of power supply. A set-and-reset type flip-flop circuit is provided between the input circuit and the counter in such a manner that the signal pulses are applied directly to one of the set and reset terminals and through an inverter to the other of the terminals. The arrangement is effective to prevent counting error which may be experienced during interruption of power supply.
Inventors:
OOSAKO KYOICHI
YAMASHITA KATSUAKI
YAMASHITA KATSUAKI
Application Number:
JP2430075A
Publication Date:
September 02, 1976
Filing Date:
February 27, 1975
Export Citation:
Assignee:
LAUREL BANK MACHINE CO
International Classes:
H03K21/00; G06F1/26; G06F12/16; G07D9/04; G11C11/413; H02J9/00; H03K21/02; H03K21/38; H03K21/40; (IPC1-7): G11C11/34; G11C29/00
Domestic Patent References:
| JPS4946096A | 1974-05-02 | |||
| JPS4840340A | 1973-06-13 | |||
| JPS5011631A | 1975-02-06 | |||
| JPS4828137A | 1973-04-13 | |||
| JPS49101071A | 1974-09-25 | |||
| JPS4826831B1 | 1973-08-16 |