Title:
TEMP. DETECTOR CIRCUIT, METHOD OF CALIBRATING TEMP. DETECTOR CIRCUIT AND SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3712537
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a temp. detector circuit wherein the dispersion at manufacturing is corrected to optimize the refresh period according to the working temp., thereby reducing the power consumption.
SOLUTION: The detector circuit 25 comprises a latch circuit 35 which latches the count value of a first counter 33 in fixed oscillation period of a second oscillator circuit 32, based on the count value of a second counter 34 after the first and second counters 33, 34 count a first and second pulse signals CK1, CK2 outputted from a first and second oscillator circuits 31, 32 different from each other in temp. dependence of the oscillation period, a ROM 38 into which data latched by the latch circuit 35 at predetermined specified working temp. are written as reference data DR, and a subtraction circuit 36 which computes the difference between comparing data DA latched by the latch circuit 35 at the time with the reference data DR in the ROM 38. A decoder 39 converts the computation result of the subtraction circuit 36 into a temp. detection signal K1 and outputs it.
Inventors:
Takaaki Furuyama
Application Number:
JP22334198A
Publication Date:
November 02, 2005
Filing Date:
August 06, 1998
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
G01K7/01; G01K15/00; G11C11/406; (IPC1-7): G01K7/01; G01K15/00; G11C11/406
Domestic Patent References:
| JP58006430A | ||||
| JP63037225A | ||||
| JP60029624A | ||||
| JP61118632A | ||||
| JP61095254A | ||||
| JP7161921A | ||||
| JP7296582A |
Attorney, Agent or Firm:
Hironobu Onda